As the density of MOS circuits increases, the requirements on alignment become more stringent. If a particular step, such as forming a contact from an upper interconnection level to a transistor is not self-aligned, then allowance in circuit layout must be made for alignment errors. Accumulation of tolerances defeats the goal of increasing the circuit density.
The art has used complex schemes, such as borderless contacts. Typically, an insulating sidewall is formed on the gate, so that the source/drain aperture may overlap the gate by some amount without causing a short. This achieves the desired result but at the price of considerable process complexity and expense.
The art has long felt the need for a simpler and less expensive process that achieves the high densities required by modern circuits.